april 1999 f dc6 321c dual n & p c hannel , digital fet general description features absolute maximum ratings t a = 25 o c unless other wise noted symbol parameter n-channel p-channel units v dss , v cc drain-source voltage, power supply voltage 25 -25 v v gss , v in gate-source voltage , 8 -8 v i d , i o drain/output current - continuous 0.68 -0.46 a - pulsed 2 -1.5 p d maximum power dissipation ( note 1a ) (note 1b ) 0.9 w 0.7 t j ,t stg operating and storage temp ature range r -55 to 150 c esd electrostatic discharge rating mil-std-883d human body model (100pf / 1500 ohm) 6 kv thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a ) 140 c/w r q jc thermal resistance, junction-to-case (note 1) 60 c/w fdc6321c .revb n-ch 25 v, 0.68 a, r ds(on) = 0.45 w @ v gs = 4.5 v p -ch -25 v, -0.46 a , r ds(on) = 1.1 w @ v gs = -4.5 v. very low level gate drive requirements allowing direct operation in 3 v circuits. v gs(th) < 1.0v. gate-source zener for esd ruggedness . >6 kv human body model replace multiple dual npn & pnp digital transistors . these dual n & p c hannel logic level enhancement mode field effect transistors are produced using fairchild 's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance. this device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. since bias resistors are not required this dual digital fet can replace several digital transistors with different bias resistors. sot-23 supersot t m -8 soic-16 so-8 sot-223 supersot t m -6 mark:.321 1 5 3 2 6 4 d1 s2 g1 d2 s1 g2 supersot -6 tm ? 1999 fairchild semiconductor corporation
electrical characteristics (t a = 25 o c unless otherwise noted ) symbol parameter conditions type min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a n-ch 25 v v gs = 0 v, i d = -250 a p-ch -25 d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c n-ch 26 mv / o c i d = -250 a , referenced to 25 o c p-ch -22 i dss zero gate voltage drain current v ds = 20 v, v gs = 0 v, n-ch 1 a t j = 5 5c 10 i dss zero gate voltage drain current v ds =-20 v, v gs = 0 v , p-ch -1 a t j = 5 5c -10 i gss gate - body leakage current v gs = 8 v, v ds = 0 v n-ch 100 na v gs = - 8 v, v ds = 0 v p-ch -100 na on characteristics (note 2) d v gs(th) / d t j gate threshold voltage temp. coefficient i d = 250 a , referenced to 25 o c n-ch -2.6 mv / o c i d = -250 a , referenced to 25 o c p-ch 2.1 v gs (th) gate threshold voltage v ds = v gs , i d = 250 a n-ch 0.65 0.8 1.5 v v ds = v gs , i d = -250 a p-ch -0.65 -0.86 -1.5 r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 0.5 a n-ch 0.33 0.45 w t j =12 5c 0.51 0.72 v gs = 2.7 v, i d = 0.2 5a 0.44 0.6 v gs = -4.5 v, i d = -0.5 a p-ch 0.87 1.1 t j =12 5c 1.21 1.8 v gs = -2.7 v, i d = -0.25 a 1.22 1.5 i d(on) on-state drain current v gs = 4.5 v, v ds = 5 v n-ch 1 a v gs = -4.5 v, v ds = -5 v p-ch -1 g fs forward transconductance v ds = 5 v, i d = 0.5 a n-ch 1.45 s v ds = -5 v, i d = -0.5 a p-ch 0.8 dynamic characteristics c iss input capacitance n-channel n-ch 50 pf v ds = 10 v, v gs = 0 v, p-ch 63 c oss output capacitance f = 1.0 mhz n-ch 28 pf p-channel p-ch 34 c rss reverse transfer capacitance v ds = -10 v, v gs = 0v, n-ch 9 pf f = 1.0 mhz p-ch 10 fdc6321c .revb
electrical characteristics (t a = 25 o c unless otherwise noted ) switching ch aracteristics (note 2 ) symbol parameter conditions type min typ max units t d(on ) turn - on delay time n-channel n-ch 3 6 ns v dd = 6 v, i d = 0.5 a, p-ch 7 20 t r turn - on rise time v gs = 4.5 v, r gen = 50 w n-ch 8 16 ns p-ch 9 18 t d(off) turn - off delay time p-channel n-ch 17 30 ns v dd = -6 v, i d = -0.5 a, p-ch 55 110 t f turn - off fall time v gen = -4.5 v, r gen = 50 w n-ch 13 25 ns p-ch 35 70 q g total gate charge n-channel n-ch 1.64 2.3 nc v ds = 5 v, i d = 0.5 a, p-ch 1.1 1.5 q gs gate-source charge v gs = 4.5 v n-ch 0.38 nc p- channel p-ch 0.32 q gd gate-drain charge v ds = -5 v, n-ch 0.45 nc i d = -0.25 a, v gs = -4.5 v p-ch 0.25 drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current n-ch 0.3 a p-ch -0.5 v sd drain-source diode forward voltage v gs = 0 v, i s = 0 .5 a (note ) n-ch 0.83 1.2 v t j =12 5c 0.69 0.85 v gs = 0 v, i s = -0 .5 a (note ) p-ch -0.89 -1.2 t j =12 5c -0.75 -0.85 notes: 1. r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where thecase thermal reference is defined as the sol der mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. fdc6321c .revb b. 180 o c/w on a 0.005 in 2 of pad of 2oz copper. a . 140 o c/w on a 0.125 in 2 pad of 2oz copper.
fdc6321c .revb typical electrical characteristics: n-channel 0 0.5 1 1.5 2 0 0.3 0.6 0.9 1.2 1.5 v , drain-source voltage (v) i , drain-source current (a) 3.5 2.7 2.5 2.0 1.5 ds d v = 4.5v gs 3.0 r ds(on ) , normalized 0 0.2 0.4 0.6 0.8 1 1.2 0.5 1 1.5 2 i , drain current (a) drain-source on-resistance v = 2.0v gs 2.7 3.0 4.5 d 3.5 2.5 figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = 4.5 v gs i =0.5 a d r , normalized ds(on) figure 3. on-resistance variation with temperature . 0 0.5 1 1.5 2 2.5 0 0.2 0.4 0.6 0.8 1 v , gate to source voltage (v) i , drain current (a) 25c 125c v = 5.0v ds gs d t = -55c j figure 5 . transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.001 0.01 0.1 1 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s figure 6 . body diode forward voltage varia tion with source current and temperature. figure 4 . on resistance variation with gate-to -source voltage. 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.4 0.8 1.2 1.6 2 v , gate to source voltage (v) id= 0.5a gs r , on-resistance (ohm) ds(on) 125c 25c
fdc6321c .revb typical electrical characteristics: n-channel (continued) 0 0.4 0.8 1.2 1.6 2 0 1 2 3 4 5 q , gate charge (nc) v , gate-source voltage (v) g gs i = 0.5a d 10v 15v v = 5v ds figure 10 . single pulse maximum power dissipation. 0.1 0.5 1 2 5 10 25 5 10 20 50 100 150 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. 0.01 0.1 1 10 100 300 0 1 2 3 4 5 single pulse time (sec) power (w) single pulse r =see note 1b t = 25c q ja a 0.1 0.2 0.5 1 2 5 10 20 40 0.01 0.03 0.1 0.3 1 5 v , drai n-source voltage (v) i , drain current (a) v = 4.5v single pulse r = see note 1b t = 25c gs q ja ds d dc 1s 10ms 100ms rds(on) limit a 1ms 100s
fdc6321c .revb typical electrical characteristics: p-channel 0 1 2 3 4 5 0 0.25 0.5 0.75 1 1.25 1.5 -v , drain-source voltage (v) -i , drain-source current (a) v = -4.5v gs ds d -2.7 -2.5 -2.0 -3.0 -1.5 -3.5 0 0.2 0.4 0.6 0.8 1 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 -i , drain current (a) drain-source on-resistance v = -2.0 v gs d r , normalized ds(on) -3.5 -4.5 -2.7 -2.5 -3.0 -4.0 figure 11. on-region characteristics . figure 12. on-resistance variation with drain current and gate voltage . -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance (ohms) j r , normalized ds(on) v = -4.5v gs i = -0.5a d figure 13. on-resistance variation with temperature . -3 -2.5 -2 -1.5 -1 -0.5 -1 -0.75 -0.5 -0.25 0 v , gate to source voltage (v) i , drain current (a) v = -5 v ds gs d t = -55c j 125c 25c figure 15 . transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.001 0.01 0.1 0.5 -v , body diode forward voltage (v) -i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s figure 16 . body diode forward voltage varia tion with source current and temperature. figure 14 . on resistance variation with gate-to - source voltage. -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 0 1 2 3 4 5 v , gate to source voltage (v) id=-0.5a gs r , on-resistance (ohm) ds(on) 125c 25c
fdc6321c .revb typical electrical characteristics: p-channel (continued) figure 19 . maximum safe operating area. 0 0.3 0.6 0.9 1.2 1.5 1.8 0 1 2 3 4 5 q , gate charge (nc) -v , gate-source voltage (v) g gs i = -0.5a d -15v v = -5v ds -10v figure 17 . gate charge characteristics . figure 2 0 . single pulse maximum power dissipation. 0.1 0.3 0.5 1 5 10 15 25 5 10 20 50 100 150 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss figure 18 . capacitance characteristics . figure 2 1 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1b .transient thermal response will change depending on the circuit board design. 0.0001 0.001 0.01 0.1 1 10 100 300 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 r(t), normalized effective duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1b q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 0.01 0.1 1 10 100 300 0 1 2 3 4 5 single pulse time (sec) power (w) single pulse r =see note 1b t = 25c q ja a 0.1 0.2 0.5 1 2 5 10 20 40 0.01 0.03 0.1 0.3 1 2 - v , drain-source voltage (v) -i , drain current (a) rds(on) limit d a dc ds 1s 100ms 10ms 1ms v = -4.5v single pulse r = see note 1b t = 25c q ja gs a
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